NDLI: Characterization analysis of a novel approach in fabrication of CMOS compatible vertical MOSFETs incorporating a dielectric pocket

Content Provider	IEEE Xplore Digital Library
Author	Riyadi, M.A. Napiah, Z.A.F.M. Saad, I. Ismail, R.
Copyright Year	2008
Description	Author affiliation: Fac. of Electr. Eng., Univ. Teknol. Malaysia, Skudai (Riyadi, M.A.; Napiah, Z.A.F.M.; Saad, I.; Ismail, R.)
Abstract	The process of making novel CMOS compatible vertical MOSFET by incorporating Dielectric Pocket (DP) is shown using virtual wafer simulation tool. The corresponding device doping profiles of a junction is highlighted and demonstrated good device profiles for the feasibility of the approach. The effect of amorph Si recrystallization as the result of different RTA time is also evaluated. Both the transfer and output characteristics of the DP vertical MOSFETs indicates a reasonable value of drive and off -leakage current (ION and IOFF), sub-threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The increasing time of RTA to 100 s shows better performance of the device than for shorter time, but in the thread-off of higher drain junction depth and leakage current.
Starting Page	639
Ending Page	642
File Size	3196955
Page Count	4
File Format	PDF
ISBN	9781424438730
DOI	10.1109/SMELEC.2008.4770407
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-25
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication MOSFETs Amorphous silicon Doping profiles Dielectric devices Dry etching CMOS process Rapid thermal annealing Anisotropic magnetoresistance Rapid thermal processing
Content Type	Text
Resource Type	Article

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