NDLI: VLSI design and analysis of low power 6T SRAM cell using cadence tool

Content Provider	IEEE Xplore Digital Library
Author	Khare, K. Khare, N. Kulhade, V.K. Deshpande, P.
Copyright Year	2008
Description	Author affiliation: M.P. Govt. Tech. Educ. (Khare, N.) \|\| Dept. of ECE, Maulana Azad Nat. Inst. of Technol., Bhopal (Khare, K.; Kulhade, V.K.; Deshpande, P.)
Abstract	CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.
Starting Page	117
Ending Page	121
File Size	2463700
Page Count	5
File Format	PDF
ISBN	9781424438730
DOI	10.1109/SMELEC.2008.4770289
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-25
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Random access memory Energy consumption Voltage Circuit stability CMOS technology Read-write memory Batteries Differential amplifiers Computer science pull up ratio 6 Transistor SRAM Cell Cell ratio
Content Type	Text
Resource Type	Article

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