NDLI: GFCG: Glitch free combinational clock gating approach in nanometer VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Sudhakar, J. Prasad, A.M. Panda, A.K.
Copyright Year	2015
Description	Author affiliation: ECE Dept., JNTUK, Kakinada, India (Prasad, A.M.) \|\| ECE Dept., Nat. Inst. of Sci. & Technol., Berahmpur, India (Panda, A.K.) \|\| ECE Dept., Vignan's Inst. of Eng. for Women, Vishakapatnam, India (Sudhakar, J.)
Abstract	Low power design is gaining prominence due to the increasing need of battery operated portable devices with high computing capability. It is the critical issue in ASIC design, as featured size is scaled down. The reliability of integrated circuit depends on the heat dissipated in the circuit. A large fraction of the power consumed is due to the clock distribution network and the high switching activity at the nodes. Clock Gating is the well-known power-saving technique used to reduce the clock power. To save power, clock gating refers to triggering the clocks in a logic block only when there is work to be done. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic. In this paper, we explain the way of Glitch reduction for ISCAS 85 bench mark circuits using combinational clock gating principle. The functionality of bench mark circuits are verified using Cadence physical flow with RTL compiler.
Starting Page	146
Ending Page	150
File Size	167724
Page Count	5
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124828
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CEC ASIC Combinational clock gating Benchmark circuits Switches Low power dissipation Logic gates ALU Registers Power dissipation Combinational circuits Clocks
Content Type	Text
Resource Type	Article

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