NDLI: Design of area and power efficient digital FIR filter using modified MAC unit

Content Provider	IEEE Xplore Digital Library
Author	Kumar, V. Nithish Nalluri, Koteswara Rao Lakshminarayanan, G.
Copyright Year	2015
Description	Author affiliation: Department of Electronics and Communication Engineering, VLSI Design Research Laboratory, National Institute of Technology, Tiruchirappalli, India (Kumar, V Nithish; Nalluri, Koteswara Rao; Lakshminarayanan, G) A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) is a well known adder for its faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which significantly reduce the area and power by eliminating the redundant logic gates at each bit level. In this paper, we propose an area and power efficient FIR filter implementation using modified Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and the modified carry select adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the Area Delay Product(ADP) of the proposed 5-tap and 9-tap filter gains an improvement of 18.26% and 13.94%, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by 16.80% and 12.54%, respectively.
Starting Page	1745
Ending Page	1748
File Size	444699
Page Count	4
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiply and Accumulate (MAC) Finite impulse response filters Carry Select Adder (CSLA) Computer architecture Digital signal processing Vegetation Logic gates FIR filter and Wallace tree multiplier Delays Adders
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design of area and power efficient digital FIR filter using modified MAC unit

Design of area and power efficient digital FIR filter using modified MAC unit

Modified wallace tree multiplier using efficient square root carry select adder

Low delay-high compact FIR filter using reduced wallace multiplier

Design of high performance Multiply-Accumulate Computation unit

Performance analysis of FIR filter using booth multiplier

Area-reduced parallel FIR digital filter structures based on Modified Winograd Algorithm

FPGA implementation of efficient FIR Filter with quantized fixedpoint coefficients

An efficient hardware based MAC design in digital filters with complex numbers

Design of area and power efficient digital FIR filter using modified MAC unit

Similar Documents

Design of area and power efficient digital FIR filter using modified MAC unit

Design of area and power efficient digital FIR filter using modified MAC unit

Modified wallace tree multiplier using efficient square root carry select adder

Low delay-high compact FIR filter using reduced wallace multiplier

Design of high performance Multiply-Accumulate Computation unit

Performance analysis of FIR filter using booth multiplier

Area-reduced parallel FIR digital filter structures based on Modified Winograd Algorithm

FPGA implementation of efficient FIR Filter with quantized fixedpoint coefficients

An efficient hardware based MAC design in digital filters with complex numbers

Design of area and power efficient digital FIR filter using modified MAC unit