NDLI: Low power flip flop merging technique by critical path delay analysis

Content Provider	IEEE Xplore Digital Library
Author	Nandhini, V. Ramprakash, K.
Copyright Year	2015
Description	Author affiliation: ECE Dept., Kumaraguru Coll. of Technol., Coimbatore, India (Ramprakash, K.) \|\| Appl. Electron. Kumaraguru Coll. of Technol., Coimbatore, India (Nandhini, V.)
Abstract	Power consumed by clocking has taken a major part of the whole design circuit. Given a design, we can reduce its power consumption by replacing several flip-flops with some multi-bit flip-flop. This may affect the performance of the original circuit because of its timing and placement capacity constraints. To overcome this problem efficiently, a technique combination table is built to enumerate possible combinations of flip-flops provided by a library. Finally, merging of flip-flops is done with help of co-ordination transformation and combination table. We can achieve better area reduction and power reduction by 37.65% The implementation of flip flop merging is done in MODELSIM software and the power analysis through Quartus IL.
Starting Page	746
Ending Page	750
File Size	601899
Page Count	5
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7125010
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Merging Clock power reduction Multi-bit flip-flop Logic gates Libraries Software Replacement Flip-flops Clocks
Content Type	Text
Resource Type	Article

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