NDLI: Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Khurshid, B. Nazir, L. Mir, R.N.
Copyright Year	2015
Description	Author affiliation: Dept. of CSE, Nat. Inst. of Technol., Srinagar, India (Khurshid, B.; Nazir, L.; Mir, R.N.)
Abstract	Modern day field programmable gate arrays (FPGA) have look-up tables (LUT) as inherent basic logic elements. With FPGAs fast moving from prototype designing to low and medium volume productions, there is an increased need for efficient utilization of these FPGA primitives. Unfortunately majority of the work concerned with FPGA implementations focus only on the technology independent (architectural) optimizations that can be done at the top level of the logic synthesis process. Once a design has been modified architecturally, its behavioral description is fed to the synthesizer that drives the logic synthesis process as per the desired cost function. Any technology dependent optimization done by the synthesizer is thus hidden from the designer. In this paper we consider the technology dependent optimization of the fixed-point bit-parallel multiplier on LUT based FPGAs. We perform technology dependent optimizations prior to the design entry phase and then use instantiation based coding styles to ensure that the optimizations remain preserved throughout the synthesis process. We have compared our implementation results against various fixed-point multipliers reported in [28]. Our implementations show substantial improvement in terms of resources utilized, critical path delays and dynamic power dissipation. An important feature of technology dependent optimizations is that it results in a simultaneous improvement of all the performance parameters. This is in contrast to the technology independent optimizations where there is always an application-driven trade-off between different performance parameters.
Starting Page	316
Ending Page	321
File Size	252292
Page Count	6
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124915
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGA Integrated circuit interconnections Technology mapping Logic gates LUT Table lookup Delays Power dissipation FPGA primitives Field programmable gate arrays Optimization Fixed-point arithmetic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Power-aware technology mapping for LUT-based FPGAs

High Efficiency Generalized Parallel Counters for Xilinx FPGAs

TDD: a technology dependent decomposition algorithm for LUT-based FPGAs

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

A test methodology for interconnect structures of LUT-based FPGAs

Heuristic technology mapper for LUT based FPGAs

Placement-based partitioning for lookup-table-based FPGAs

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs

t-Private logic synthesis on FPGAs

Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs

Similar Documents

Power-aware technology mapping for LUT-based FPGAs

High Efficiency Generalized Parallel Counters for Xilinx FPGAs

TDD: a technology dependent decomposition algorithm for LUT-based FPGAs

Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs

A test methodology for interconnect structures of LUT-based FPGAs

Heuristic technology mapper for LUT based FPGAs

Placement-based partitioning for lookup-table-based FPGAs

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs

t-Private logic synthesis on FPGAs

Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs