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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shinde, J. Salankar, S.S. |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electronics & Telecommunication Engineering J.L. Chaturvedi College of Engineering, Nagpur (Shinde, J.; Salankar, S.S.) |
| Abstract | Clock gating is one of the power-saving techniques used on the Pentium 4 processor and in next generation processors. To save power, clock gating refers to activating the clocks in a logic block only when there is work to be done. From the earliest days of the Pentium 4 processor design, power consumption was a concern. The clock gating concept isn't a new one; however, the Pentium 4 processor used this technology to a large extent. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic. The work in this paper investigates the various clock gating techniques that can be used to optimise power in VLSI circuits at RTL level and various issues involved while applying this power optimization techniques at RTL level. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 247727 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457711107 |
| e-ISBN | 9781457711091 |
| DOI | 10.1109/INDCON.2011.6139440 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-16 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Latches Power demand core dynamic power dissipation latch based clock gating Clock Gating (CG) Switches Logic gates latch free clock gating Optimization Clocks Flip-flops |
| Content Type | Text |
| Resource Type | Article |
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