NDLI: Improvement of test data compression using combined encoding

Content Provider	IEEE Xplore Digital Library
Author	Mirthulla, S. Arulmurugan, A.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., Kongu Eng. Coll., Perundurai, India (Mirthulla, S.; Arulmurugan, A.)
Abstract	Developments in process technology have led to the design of systems with millions of transistors on a single chip and it has resulted in an increase of test data required to test the circuits. Conventional external testing processes involve storing all test vectors and test responses on the automatic test equipment (ATE) memory. The test data volume for the scan-based test is normally very large due to its single pattern length generated using a combinational automatic test pattern generation (ATPG) tool. The test application time depends on the amount of test data stored on ATE, the time required to transfer the test data from ATE to the core and length of the scan chain. But these testers have limited memory, speed and I/O channels. Efficient test data reduction techniques can reduce the testing time, test power and ATE memory requirements. Three multistage compression techniques are introduced to reduce the test data volume in scan-test applications. The three encoding schemes namely equal run-length coding (ERLC), extended frequency directed run-length (EFDR) coding, alternating variable run-length (AVR) is used for computing the data. These encoding scheme together with nine coded (9C) technique enhance the test compression ratio. In the first stage, pre-generated test cubes with unspecified bits are encoded using nine-coded (9C) scheme. Later the three encoding schemes utilize the properties of compressed data to enhance the test compression. This multistage compression is effective especially when the percentage of don't care in a test set is very high. The experimental result obtained from ISCAS'89 benchmark circuit confirms the average compression ratio of 46%, 52%, 57% with the proposed 9C-ERLC, 9C-EFDR, 9C-AVR codes respectively.
Starting Page	635
Ending Page	638
File Size	157823
Page Count	4
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124985
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Test data compression Very large scale integration Automatic test pattern generation Benchmark testing Huffman coding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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