NDLI: Design and analysis of different types SRAM cell topologies

Content Provider	IEEE Xplore Digital Library
Author	Kiran, P. N. Vamsi Saxena, Nikhil
Copyright Year	2015
Description	Author affiliation: Dept. of CTM of ITM Universe Gwalior, India (Saxena, Nikhil) \|\| ITM Universe, Gwalior, India (Kiran, P N Vamsi) In this paper, we design different type of SRAM cells. This paper compares the performance of five SRAM cell topologies, which include the conventional 6T, 7T, 8T, 9T and the 10T SRAM cell implementations. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. In 10T SRAM cell implementation results, reduced leakage power and leakage current by 36% and 64% respectively, the read stability is increased by 13% over conventional 6T, 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. The aim of this paper is to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.
Starting Page	167
Ending Page	173
File Size	582307
Page Count	7
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET Leakage Current Low Power Read Stability Logic gates Leakage Power SRAM cells SRAM Cell Circuit stability Leakage currents
Content Type	Text
Resource Type	Article

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