NDLI: An efficient architecture of transparent-scan sequences among logic blocks using T-algorithm

Content Provider	IEEE Xplore Digital Library
Author	Rubini, D. Esther, T.
Copyright Year	2015
Abstract	An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage. In order to overcome above problems a new technique called T-algorithm is proposed. This algorithm reduces the clocking in a circuit and optimizes the testing architecture. The testing architecture consists of Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) blocks. The optimization process is mainly focused on the reduction of clock levels, instead of applying clock pulse to each flip-flop separately, the output taken from the MUX is applied to next flip-flops.
Starting Page	1000
Ending Page	1004
File Size	181387
Page Count	5
File Format	PDF
e-ISBN	9781479972258
DOI	10.1109/ECS.2015.7124729
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-02-26
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	T-algorithm Launch-off-capture Launch-off-shift Computer architecture Registers Delays Circuit faults Testing Clocks Flip-flops Transparent-scan
Content Type	Text
Resource Type	Article

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