NDLI: Balanced Low Noise High Dynamic Photodiode Interface for Automotive

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Table of contents

Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs

A Large-Scale Reconfigurable Analog Signal Processor (RASP) IC

Determination of Power Gating Granularity for FPGA Fabric

Reconfigurable Asynchronous Logic

A 50-GHz Phase-Locked Loop in 130-nm CMOS

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

Passive & Active Control of Regenerative Standing & Soliton Waves

A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider

Incremental Delta-Sigma Structures for DC Measurement: an Overview

A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers

A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique

A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter

A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization

Jitter And Signaling Test For High-Speed Links

Paper withdrawn

A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters

Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS

A Highly Integrated Power Management IC for Advanced Mobile Applications

A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS

Design and implementation of a reconfigurable heterogeneous multiprocessor SoC

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC

Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry

A Multi-Nodes Human Body Communication Sensor Network Control Processor

Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip

A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee

A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter

Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS

Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter

A Novel DAC Based Switching Power Amplifier for Polar Transmitter

A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure

Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors

Low Power Approaches to High Speed CMOS Current Steering DACs

An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC

A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications

Implications of Proximity Effects for Analog Design

Verification of Complex Analog Integrated Circuits

On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels

Predictive Modeling of the NBTI Effect for Reliable Design

Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage Device

Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators

Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A

A Phase-Domain Continuous-Time $2^{nd}-Order$ ΔΣ Frequency Digitizer

A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration

A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier

10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC

A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT Technology

A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS

A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays

ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor

Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications

1.56 GHz On-chip Resonant Clocking in 130nm CMOS

Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation

A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics

An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling

A Floating-gate Based Low-Power Capacitive Sensing Interface Circuit

Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

An Integrated 90V Switch Array for Medical Ultrasound Applications

Towards a Wearable Electronic Nose Chip

A 1V 420μW 32-channel Cortical Signal Interface

A 3D Multi-Aperture Image Sensor Architecture

GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling

A Driving Scheme for AMOLED Displays Based on Current Feedback

Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories

A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme

180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory

A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs

A 0.13 μm Low-power Race-free Programmable Logic Array

An Energy Scalable Computational Array for Sensor Signal Processing

Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency

VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel

A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor

Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators

Width Quantization Aware FinFET Circuit Design

Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A

IO Clock Network Skew & Performance Analysis: A Pentium-D Case Study

Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked Dividers

The Backward-traversing Relaxation Algorithm for Circuit Simulation

Yield and Cost Modeling for 3D Chip Stack Technologies

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs

CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement

In Situ Evaluation Method for On-Chip Inductors Using Oscillator Response

A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage

A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications

Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study

An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications

X/Ku Band CMOS LNA Design Techniques

A 60GHz Phased Array in CMOS

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology

A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS

FEXT Crosstalk Cancellation for High-Speed Serial Link Design

A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA

A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers

Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator

Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI

Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM

Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling

Low Cost Test of High Bandwidth Embedded Memories

High-Temperature, High Reliability EEPROM Design For Automotive Applications

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

Integrated MEMS Switches for Leakage Control of Battery Operated Systems

CNT based mechanical devices for ULSI memory

Nucleic Acid Extraction, Amplification, and Detection on Si-based Microfluidic Platforms

Silicon Integrated Circuits Incorporating Antennas

Frequency-Based Measurement of Mismatches Between Small Capacitors

A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology

A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications

A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

Low-Power Design of Pipeline A/D Converters

A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC

Digital Signal Processing for RF at 45-nm CMOS and Beyond

Delta-Sigma Modulation in Direct Digital Frequency Synthesis

OFDM modulator with digital IF and on-chip D/A-converter

Neuromorphic Vision Systems for Mobile Applications

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile Terminals

A GFLOPS Vector-DSP for Broadband Wireless Applications

SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design

The UltraSPARC T1 Processor: CMT Reliability

A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop

Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

Robust Inductor Design for RF Circuits

Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications

Balanced Low Noise High Dynamic Photodiode Interface for Automotive

On-chip Digitally Tunable High Voltage Generator for Electrostatic Control of Micromechanical Devices

Die Stacking Technology for Terabit Chip-to-Chip Communications

Wireline equalization using pulse-width modulation

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS

A 1.6Gbps Digital Clock and Data Recovery Circuit

A Sub-i V Low-Noise Bandgap Voltage Reference

A Compact Programmable CMOS Reference With ±40μV Accuracy

A Transient-Enhanced 20μA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation

Compact outside-rail circuit structure by single-cascode two-transistor topology

Enhancing Productivity by Continuously Improving Standard Compact Models

A Web Tool for Interactive Exploration of Analog Design Tradeoffs

Circuit Optimization Using Scale Based Sensitivities

A 4-Channel High-Precision Constant Current Control ASIC for Automotive Transmission Applications

Ditherng Skip Modulator with a Width Controller for Ultra-wide-load High-Efficiency DC-DC Converters

Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array

Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays

A 104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork Microgyroscopes

Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical Microsystems

Notice of Violation of IEEE Publication Principles
A Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors

An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback

Mutual Injection Pulling Between Oscillators

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges

Recent Advances in III-V Electronics

Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices

SiGe BiCMOS Trends - Today and Tomorrow

Advances and Challenges in Flip-Chip Packaging

Compact modeling of noise in CMOS

A Scalable Model Methodology for Octagonal Differential and Single-Ended Inductors

Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects

A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model

Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs

First-Harmonic Injection-Locked Ring Oscillators

Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation

Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators

A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery

Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance

A Low Jitter Multi-Phase PLL with Capacitive Coupling

A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur

Integrated VCO Design for MICS Transceivers

A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading

Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

Digital RF Processor Techniques for Single-Chip Radios

A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers

A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System

A Distributed RF Front-End for UWB Receivers

A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC

Active On-Die Suppression of Power Supply Noise

A Fully Integrated DC/DC Converter for Tunable RF Filters

A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming

A Unity-Gain Buffer with Reduced Offset and Gain Error

A 19-GHz Broadband Amplifier Using a $g_{m}-Boosted$ Cascode in 0.18-μm CMOS

A 0.6V Highly Linear Switched-R-MOSFET-C Filter

Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration

A Low Phase Noise 100MHz Silicon BAW Reference Oscillator

EDA Challenges in Nano-scale Technology

Statistical and Corner Modeling of Interconnect Resistance and Capacitance

Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells

Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation

Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform

Crosstalk Reduction with Nonlinear Transmission Lines for High-Speed VLSI System

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Balanced Low Noise High Dynamic Photodiode Interface for Automotive

Content Provider	IEEE Xplore Digital Library
Author	Koudar, I.
Copyright Year	2006
Description	Author affiliation: AMIS Mixed Signal Design Center, Brno (Koudar, I.)
Abstract	A high performance balanced photodiode sensor interface for the automotive industry is introduced. A novel switched current based architecture provides 100dB input current dynamic range. Correlated double sampling technique is used for 1/f noise suppression in the MOS input circuitry. Sigma delta ADC (13 bit) is used. The measured SNR is >66dB. Embedded offset compensation supports fast 236mus conversion cycle per channel. Mixed signal chip architecture is described. EMC emissions measurement results meet the strict automotive limits
Starting Page	579
Ending Page	582
File Size	4518931
Page Count	4
File Format	PDF
ISBN	1424400759
DOI	10.1109/CICC.2006.320992
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Vehicle dynamics Photodiodes Automotive engineering Circuit noise Semiconductor device measurement Dynamic range Sampling methods Delta-sigma modulation Signal to noise ratio Electromagnetic compatibility SNR Balanced photodiode sensor interface 100dB input current dynamic range correlated double sampling 1/f noise mixed signal chip
Content Type	Text
Resource Type	Article

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