NDLI: Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array

Content Provider	IEEE Xplore Digital Library
Author	Sang-Min Lee Hyimsik Park Wooley, B.A.
Copyright Year	2006
Description	Author affiliation: Center for Integrated Syst., Stanford Univ., CA (Sang-Min Lee; Hyimsik Park; Wooley, B.A.)
Abstract	A per-pixel floating-point, dual-slope A/D converter (ADC) array for a 16 times 16 long wavelength infrared detector array has been integrated in a 0.18-mum CMOS technology. To achieve a high dynamic range and high frame rate simultaneously, an electronic shutter is combined with an ADC for each pixel. A unique method of comparator offset cancellation, employing an integration capacitor with digital calibration, improves the uniformity of the array. The experimental prototype achieves a 19-bit dynamic range and 8-bit resolution at 3 kfps, with a power consumption of only 7 muW/pixel. Each per-pixel ADC occupies 4000 $mum^{2}$ and is well-suited to 3-dimensional integration
Starting Page	647
Ending Page	650
File Size	313485
Page Count	4
File Format	PDF
ISBN	1424400759
DOI	10.1109/CICC.2006.320864
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic range Capacitors Counting circuits Sampling methods Voltage Clocks Fault location Infrared detectors Sensor arrays CMOS technology 3-D integration A/D converter per-pixel ADC floating-point ADC dual-slope ADC infrared focal plane array
Content Type	Text
Resource Type	Article

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