NDLI: Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays

Content Provider	IEEE Xplore Digital Library
Author	Chul Bum Kim Byung-Hyuk Kim Yong Soo Lee Han Jung Hee Chul Lee
Copyright Year	2006
Description	Author affiliation: Adv. Inst. of Sci. & Technol., Daejeon (Chul Bum Kim)
Abstract	This paper presents a novel CMOS charge transfer readout circuit for X-ray time delay and integration (TDI) arrays with a depth of 64. The proposed circuit uses a charge transfer readout similar to CCD; thus, the summing of the signal charges can be implemented easily compared with other typical CMOS readout circuits for TDI arrays. The weakness of TDI arrays related to defective pixels can be solved by integrating a dead pixel elimination circuit. In addition, the proposed method can be applied to a TDI arrays with large depths, so a high signal to noise ratio (SNR) can be acquired. The readout chip has been fabricated using a 0.6 mum standard CMOS process for 150times64 CdTe X-ray detector arrays. It was found that the readout circuit can effectively increase the charge storage capacity up to $1.6times10^{9}$ electrons, and then provide an SNR improved by a factor of approximately 8
Starting Page	651
Ending Page	654
File Size	483618
Page Count	4
File Format	PDF
ISBN	1424400759
DOI	10.1109/CICC.2006.320865
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge transfer Circuits Delay effects Charge coupled devices Signal to noise ratio X-ray detectors X-ray imaging CMOS technology Sensor arrays Digital systems
Content Type	Text
Resource Type	Article

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