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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Leon, A.S. Langley, B. Jinuk Luke Shin |
| Copyright Year | 2006 |
| Description | Author affiliation: Sun Microsystems Inc., Sunnyvale, CA (Leon, A.S.; Langley, B.; Jinuk Luke Shin) |
| Abstract | Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power, cooling and reliability in today's datacenters. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture to deliver high performance and reliability in a low power and thermal envelope. The UltraSPARC T1 processor combines eight 4-threaded 64b cores, a high bandwidth interconnect crossbar, a shared 3MB L2 cache and four double-width DDR2 DRAM interfaces. Implemented in 90nm CMOS technology, the $378mm^{2}$ die consumes only 63W at 1.2GHz. Beyond the ability of CMT to optimize throughput performance, this paper highlights the advantages of CMT in the areas of power and thermal control, reliability, RAS, and design robustness, describing key features of the design relevant to each of these topics |
| Starting Page | 555 |
| Ending Page | 562 |
| File Size | 664788 |
| Page Count | 8 |
| File Format | |
| ISBN | 1424400759 |
| DOI | 10.1109/CICC.2006.320989 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-09-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Throughput CMOS technology Process design Cooling Power generation Multithreading Computer architecture Bandwidth Random access memory Design optimization throughput performance Channel Hot Carrier (CHC) Chip MultiThreading (CMT) Electromigration (EM) Error Correcting Code (ECC) Gate-Oxide Integrity (GOI) Negative Bias Temperature Instability (NBTI) Niagara processor Reliability Availability Serviceability (RAS) Soft Error Rate (SER) redundancy UltraSPARC T1 alpha particles chip reliability low power multicore parity protection power management reliability-aware thermal management |
| Content Type | Text |
| Resource Type | Article |
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