NDLI: Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

Content Provider	IEEE Xplore Digital Library
Author	Arsovski, I. Wistort, R.
Copyright Year	2006
Description	Author affiliation: IBM Silicon Solutions, Essex Junction, VT (Arsovski, I.; Wistort, R.)
Abstract	A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V
Starting Page	453
Ending Page	456
File Size	4215744
Page Count	4
File Format	PDF
ISBN	1424400759
DOI	10.1109/CICC.2006.320819
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer aided manufacturing CADCAM Timing Uncertainty Automatic testing Time measurement Power measurement Energy consumption Hardware Robustness
Content Type	Text

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