NDLI: FEXT Crosstalk Cancellation for High-Speed Serial Link Design

Content Provider	IEEE Xplore Digital Library
Author	Kin-Joe Sham Ahmadi, Mahmoud Rezci Bommalingaiahnapallya Shubha Talbot, G. Harjani, R.
Copyright Year	2006
Description	Author affiliation: Minnesota Univ., Minneapolis, MN (Kin-Joe Sham; Mahmoud Rezci Ahmadi; Shubha Bommalingaiahnapallya)
Abstract	We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX pre-emphasis, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMC's 0.18mum CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2times reduction in line separation, FEXT cancellation can successfully reduce jitter by 51.2 %UI and widen the eye by 14.5%. The 2.5 times 1.5 $mm^{2}$ core consumes 630mW per lane at 12.8Gbps with a 1.8V supply
Starting Page	405
Ending Page	408
File Size	5807497
Page Count	4
File Format	PDF
ISBN	1424400759
DOI	10.1109/CICC.2006.320971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Transmitters Jitter CMOS technology Transceivers Intersymbol interference Interference cancellation Semiconductor device modeling Semiconductor device measurement Prototypes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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