NDLI: Full-chip inter-die parasitic extraction in face-to-face-bonded 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Yarui Peng Taigon Song Petranovic, D. Sung Kyu Lim
Copyright Year	2015
Description	Author affiliation: Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA (Yarui Peng; Taigon Song; Sung Kyu Lim) \|\| Mentor Graphics, Fremont, CA, USA (Petranovic, D.)
Abstract	Face-to-face (F2F) bonded 3D ICs are promising design solutions. However, because of the short die-to-die distance, direct coupling between the metal layers of the top and bottom dies introduces severe signal integrity problems that call for accurate extraction. This study is the first to demonstrate and compare three parasitic extraction methods of F2F-bonded 3D ICs. One is traditional die-by-die extraction, which cannot handle inter-die coupling and E-field sharing. We propose another method, holistic extraction, which treats all layers from both dies simultaneously and captures all inter-die coupling at the cost of high Layout Versus Schematic (LVS) complexity. We also propose an in-context extraction method that accounts for interface layers between dies. Carefully handling double-counting and surface layers issues, in-context extraction is LVS-friendly without losing accuracy. Full-chip analyses show that both of our extraction methods are highly accurate and able to handle various metal layers in several process nodes. It also corrects timing, power, and signal integrity errors introduced by die-by-die extraction. In-context extraction with two interface layers is highly accurate and efficient with an error of 0.9% for total ground capacitance and 0.8% for total coupling capacitance.
Starting Page	649
Ending Page	655
File Size	1782012
Page Count	7
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372631
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Capacitance Couplings Wires Metals Bonding Libraries extraction Face-to-face 3D IC die-by-die holistic in-context
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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