NDLI: Mixed cell-height implementation for improved design quality in advanced nodes

Content Provider	IEEE Xplore Digital Library
Author	Dobre, S. Kahng, A.B. Jiajia Li
Copyright Year	2015
Description	Author affiliation: Qualcomm Technol., Inc., San Diego, CA, USA (Dobre, S.) \|\| ECE Depts., UC San Diego, La Jolla, CA, USA (Kahng, A.B.; Jiajia Li)
Abstract	In advanced nodes, standard-cell libraries can be developed with different cell heights (e.g., in FinFET technology, corresponding to different numbers of fins). Larger cell heights provide higher drive strengths, but at the cost of larger area and power consumption as well as pin capacitance. Cells with smaller heights are relatively smaller in area, but have weaker drive strengths and are more likely to suffer from routing congestion and pin accessibility issues. Existing design methodologies and tool flows are able to mix cells with different heights at the block level (i.e., each block contains cells of a particular cell height). To our knowledge, no design methodology in the literature mixes cells of different heights in a fine-grained manner. In this work, we propose a novel physical design optimization flow to implement design blocks with mixed cell heights in a fine-grained manner. Our optimization resolves the “chicken-and-egg” loop between floorplan site definition and the optimized choices of cell heights after placement. Comprehending the constraints and costs of mixing cells of different heights (e.g., the “breaker cell” area overheads of row alignment between sub-blocks of 8T and 12T cell rows), our optimization achieves 25% area reduction versus 12T-only implementation while maintaining the same performance, and 20% performance improvement versus 8T-only implementation while maintaining similar total cell area.
Starting Page	854
Ending Page	860
File Size	1816500
Page Count	7
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372660
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Optimization Yttrium Capacitance Routing Layout
Content Type	Text
Resource Type	Article

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