NDLI: Acceleration of nested conditionals on CGRAs via trigger scheme

Content Provider	IEEE Xplore Digital Library
Author	Shouyi Yin Pengcheng Zhou Leibo Liu Shaojun Wei
Copyright Year	2015
Description	Author affiliation: Inst. of Microelectron., Tsinghua Univ., Beijing, China (Shouyi Yin; Pengcheng Zhou; Leibo Liu; Shaojun Wei)
Abstract	Coarse-Grained Reconfigurable Architecture (CGRA) is a promising accelerator when considering both high performance and high power-efficiency. One of the challenges that CGRAs are confronting is to accelerate loops with control flow (if-then-else structures). Existing techniques employ predication to accelerate the conditionals but cannot accelerate nested conditionals efficiently. The state-of-the-art method dual issue scheme issues instructions from both the branch paths and then executes only the instructions from the path chosen by a predicate. But it also cannot handle nested conditionals. In this paper, we propose a solution to map loops with nested conditionals on a CGRA for the Triggered Instruction Architecture (TIA) paradigm - in which lacks compiler support. Experimental results show:We can accelerate loop kernels with nested conditionals via trigger scheme average of 1.41×, 1.79× and 1.29× better performance compared to partial predication, full predication and dual issue scheme respectively.
Starting Page	597
Ending Page	604
File Size	1491310
Page Count	8
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372624
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Registers Junctions Computer architecture Kernel Field programmable gate arrays Power demand
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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