NDLI: A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration

Content Provider	IEEE Xplore Digital Library
Author	Wei Zuo Kemmerer, W. Jong Bin Lim Pouchet, L.-N. Ayupov, A. Taemin Kim Kyungtae Han Deming Chen
Copyright Year	2015
Description	Author affiliation: Comput. Sci. & Eng. Dept., Ohio State Univ., Columbus, OH, USA (Pouchet, L.-N.) \|\| Electr. & Comput. Eng. Dept., Univ. of Illinois, Urbana, IL, USA (Wei Zuo; Kemmerer, W.; Jong Bin Lim; Deming Chen) \|\| Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA (Ayupov, A.; Taemin Kim; Kyungtae Han)
Abstract	With the prevalence of System-on-Chips there is a growing need for automation and acceleration of the design process. A classical approach is to take a C/C++ specification of the application, convert it to a SystemC (or equivalent) description of hardware implementing this application, and perform successive refinement of the description to improve various design metrics. In this work, we present an automated SystemC generation and design space exploration flow alleviating several productivity and design time issues encountered in the current design process. We first automatically convert a subset of C/C++, namely affine program regions, into a full SystemC description through polyhedral model-based techniques while performing powerful data locality and parallelism transformations. We then leverage key properties of affine computations to design a fast and accurate latency and power characterization flow. Using this flow, we build analytical models of power and performance that can effectively prune away a large amount of inferior design points very fast and generate Pareto-optimal solution points. Experimental results show that (1) our SystemC models can evaluate system performance and power that is only 0.57% and 5.04% away from gate-level evaluation results, respectively; (2) our latency and power analytical models are 3.24% and 5.31% away from the actual Pareto points generated by SystemC simulation, with 2091x faster design-space exploration time on average. The generated Pareto-optimal points provide effective low-power design solutions given different latency constraints.
Starting Page	357
Ending Page	364
File Size	1318179
Page Count	8
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372592
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Unified modeling language Analytical models Space exploration Hardware Software Parallel processing
Content Type	Text
Resource Type	Article

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