NDLI: Simultaneous guiding template optimization and redundant via insertion for directed self-assembly

Content Provider	IEEE Xplore Digital Library
Author	Shao-Yun Fang Yun-Xiang Hong Yi-Zhen Lu
Copyright Year	2015
Description	Author affiliation: Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Yun-Xiang Hong) \|\| Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan (Shao-Yun Fang; Yi-Zhen Lu)
Abstract	In sub-10 nm technology nodes, next generation lithography technologies are urgently required, and the diblock copolymer directed self-assembly (DSA) technology has shown its strong potential for contact/via layer fabrication. In addition, post-layout redundant via insertion has become a necessary step to guarantee sufficient yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously deteriorate via manufacturability. In contrast, a sophisticated DSA-aware redundant via insertion algorithm may not only enhance circuit reliability but also improve DSA manufacturability. In this paper, we propose the first work of simultaneous guiding template optimization and redundant via insertion for DSA. An optimal integer linear programming (ILP)-based algorithm and an efficient graph-based approach are provided. To facilitate the development of the ILP formulation, a systematic approach is proposed to determine whether a via is manufacturable with DSA. In addition, reduction techniques are presented to greatly reduce the computational complexity of ILP. For the graph-based approach, all feasible via patterns composed of original vias and redundant vias are identified. Then, the original problem is transformed into a graph formulation and efficiently optimized. Experimental results show that both of our two algorithms can effectively optimize via manufacturability and maximize the redundant via insertion rate within reasonable computation time.
Starting Page	410
Ending Page	417
File Size	797643
Page Count	8
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372599
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lithography Optimization Integrated circuit reliability Metals Fabrication Layout
Content Type	Text
Resource Type	Article

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