NDLI: TAU 2015 contest on incremental timing analysis

Content Provider	IEEE Xplore Digital Library
Author	Jin Hu Schaeffer, G. Garg, V.
Copyright Year	2015
Description	Author affiliation: IBM Syst. & Technol. Group, Hopewell Junction, NY, USA (Jin Hu; Schaeffer, G.) \|\| Cadence Design Syst., San Jose, CA, USA (Garg, V.)
Abstract	Among timing analysis applications, timing-driven operations are imperative for the success of optimization flows, such as placement, routing, logic synthesis, and physical synthesis. Optimization transforms change the design, and therefore have the potential to significantly affect timing information. As such, timing must be kept current to ensure slack integrity and timing closure. For reasonable turnaround and performance, the timer should incrementally update the affected portion of the design. The aim of the TAU 2015 timing contest is to seek novel ideas for incremental timing analysis by: (i) introducing the concept and motivating the importance of incremental timing analysis, (ii) encourage novel parallelization techniques (including multi-threading), and (iii) facilitating the creation of an incremental timing analysis framework with benchmarks to further advance this research area.
Starting Page	882
Ending Page	889
File Size	761569
Page Count	8
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372664
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Integrated circuit interconnections Integrated circuit modeling Optimization Logic gates
Content Type	Text
Resource Type	Article

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