NDLI: Scalable detailed placement legalization for complex sub-14nm constraints

Content Provider	IEEE Xplore Digital Library
Author	Kwangsoo Han Kahng, A.B. Hyein Lee
Copyright Year	2015
Description	Author affiliation: CSE Depts., UC San Diego, La Jolla, CA, USA (Kahng, A.B.) \|\| ECE Depts., UC San Diego, La Jolla, CA, USA (Kwangsoo Han; Hyein Lee)
Abstract	Technology scaling to 10nm and below introduces complex intra-row and inter-row constraints in standard-cell detailed placement. Examples of such constraints are found in rules for drain-drain abutment, minimum implant region area and width, oxide diffusion (OD) notching and jogging, etc. Typically, these rules are too complex for the normal global-detailed placement flow to fully consider. On the other hand, guardbanding the library cell design so that arbitrary cell placement adjacencies are all “correct by construction” has increasingly high area cost. This motivates the introduction of a final legalization phase for standard-cell placement tools in advanced (particularly 10nm and 7nm) foundry nodes. In this work, we develop a mixed integer-linear programming (MILP)-based placer, called DFPlacer, for final-phase design rule violation (DRV) fixing. DFPlacer finds (near-)DRV-free solutions considering various complex layout constraints including minimum implant width, drain-drain abutment, and oxide diffusion jogs. To overcome the runtime limitation of MILP-based approaches, we implement a distributable optimization strategy based on partitioning of the block layout into windows of cells that can be independently legalized. Using layouts in an abstracted 7nm library, we find that DFPlacer fixes 99% of DRVs on average with minimal impacts on area and timing. We also study an area-DRV tradeoff between two types of standard-cell library strategies, namely, with and without dummy poly gates.
Starting Page	867
Ending Page	873
File Size	840776
Page Count	7
File Format	PDF
e-ISBN	9781467383882
DOI	10.1109/ICCAD.2015.7372662
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Implants Optimization Logic gates Layout Libraries Standards Transistors
Content Type	Text
Resource Type	Article

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