NDLI: Hardware protection and authentication through netlist level obfuscation

Content Provider	IEEE Xplore Digital Library
Author	Chakraborty, R.S. Bhunia, S.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH (Chakraborty, R.S.; Bhunia, S.)
Abstract	Hardware intellectual property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs and to prevent revenue loss due to IP piracy. In this paper, we propose a novel design methodology for hardware IP protection and authentication using netlist level authentication. The proposed methodology can be integrated in the SoC design and manufacturing flow to provide hardware protection to the IP vendors, the chip designer, and the system designer. Simulation results on ISCAS-89 benchmark circuits show that we can achieve high levels of security through a well-formulated obfuscation scheme at less than 10% area overhead under delay constraint.
Starting Page	674
Ending Page	677
File Size	616214
Page Count	4
File Format	PDF
ISBN	9781424428199
ISSN	10923152
DOI	10.1109/ICCAD.2008.4681649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Protection Authentication Intellectual property System-on-a-chip Design methodology Manufacturing Circuit simulation Security Delay hardware protection Design for security IP piracy hardware authentication hardware obfuscation
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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