NDLI: PaRS: Fast and near-optimal grid-based cell sizing for library-based design

Content Provider	IEEE Xplore Digital Library
Author	Tai-Hsuan Wu Davoodi, A.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI (Tai-Hsuan Wu; Davoodi, A.)
Abstract	We propose PaRS, a parallel and randomized tool which solves the discrete gate sizing (cell sizing) problem on a grid. PaRS is formulated based on an optimization framework known as Nested Partitions which uses parallelism and randomization from a novel perspective to better identify the optimization direction. It achieves near-optimal solutions for minimizing total power and area subject to meeting a delay constraint. The embarrassingly-parallel nature of PaRS makes it highly efficient. We show small algorithm run-times, in at most minutes for circuits with over 47,000 cells. We make comparison with the optimal solution generated by a custom and parallel branch-and-bound algorithm. Consequently, we are able to generate the optimal solution within hours. While the optimal algorithm uses up to 200 nodes in our grid, PaRS achieves its speedups and near-optimal solutions using only 20 nodes.
Starting Page	107
Ending Page	111
File Size	149273
Page Count	5
File Format	PDF
ISBN	9781424428199
ISSN	10923152
DOI	10.1109/ICCAD.2008.4681559
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Runtime Libraries Sampling methods Partitioning algorithms Circuits Parallel processing Delay estimation Grid computing Design engineering Delay effects
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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