NDLI: Integrated code and data placement in two-dimensional mesh based chip multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Yemliha, T. Srikantaiah, S. Kandemir, M. Karakoy, M. Irwin, M.J.
Copyright Year	2008
Description	Author affiliation: Syracuse Univ., Syracuse, NY (Yemliha, T.) \|\| Pennsylvania State Univ., University Park, PA (Srikantaiah, S.; Kandemir, M.; Irwin, M.J.) \|\| Imperial Coll. London, London (Karakoy, M.)
Abstract	As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on the current performance trajectory for both high-end systems and embedded systems. Since future technologies offer the promise of being able to integrate billions of transistors on a chip, the prospects of having hundreds to thousands of processors on a single chip along with an underlying memory hierarchy and an interconnection system is entirely feasible. This paper proposes a compiler directed integrated code and data placement scheme for two-dimensional mesh based CMP architectures. The proposed approach uses a Code-Data Affinity Graph (CDAG) to represent the relationship between loop iterations and array data and then assigns the sets of loop iterations to processing cores and sets of data blocks to on-chip memories. During the mapping process, the on-chip memory capacity and load imbalance across different cores and the topology of the NoC are taken into account. In this paper, we present two variants of our approach: depth-first placement (DFP) and breadth-first placement (BFP), and compare them to three alternate code/data mapping schemes. The experimental evaluation shows that our CDAG based placement schemes are very successful in practice, achieving average performance improvements of 19.9% (DFP) and 16.8% (BFP), and average energy improvements of 29.7% (DFP) and 27.8% (BFP).
Starting Page	583
Ending Page	588
File Size	1581586
Page Count	6
File Format	PDF
ISBN	9781424428199
ISSN	10923152
DOI	10.1109/ICCAD.2008.4681635
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Educational institutions Embedded system Topology Network-on-a-chip Network interfaces Program processors Programming profession Memory management Costs
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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