NDLI: Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure

Content Provider	IEEE Xplore Digital Library
Author	Huan Ren Dutt, S.
Copyright Year	2008
Description	Author affiliation: Dept. of ECE, Univ. of Illinois-Chicago, Chicago, IL (Huan Ren; Dutt, S.)
Abstract	We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay under area constraints by simultaneously considering the benefits and costs of all transforms (as opposed to considering them sequentially after applying each transform). The circuit transforms we employ include, but are not limited to, incremental placement, two types of buffer insertion, cell resizing and cell replication. The problem is modeled as a min-cost network flow problem, in which nodes represent circuit transform options. By carefully determining the structure of the network graph and the cost of each arc, a set of near-optimal transform options can be obtained as those whose corresponding nodes in the network graph have the min-cost flow passing through them. We also tie the transform selection network graph to a detailed placement network graph with TD arc costs for cell movements. This enables our algorithms to incorporate considerations of detailed placement cost for each synthesis transform along with the basic cost of applying the transform in the circuit. We have tested our algorithms on three sets of benchmarks under 3-10% area increase constraints, and obtained up to 48% and an average of 27.8% timing improvement. Our average improvement is relatively 40% better (8.2% better by an absolute measure) than applying the same set of transforms in a good sequential order that is used in many current techniques. Considering only synthesis transforms (no replacement), our technique is relatively 50% better than the sequential approach.
Starting Page	93
Ending Page	100
File Size	254169
Page Count	8
File Format	PDF
ISBN	9781424428199
ISSN	10923152
DOI	10.1109/ICCAD.2008.4681557
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Costs Integrated circuit synthesis Discrete transforms Circuit synthesis Network synthesis Delay Joining processes Circuit testing Benchmark testing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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