NDLI: Gate sizing using incremental parameterized statistical timing analysis

Content Provider	IEEE Xplore Digital Library
Author	Guthaus, M.R. Venkateswarant, N. Visweswariaht, C. Zolotov, V.
Copyright Year	2005
Description	Author affiliation: Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA (Guthaus, M.R.; Venkateswarant, N.; Visweswariaht, C.; Zolotov, V.)
Abstract	As technology scales into the sub-90 nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a first-order linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces run-time and improves area and performance. The gate sizing results show a significant improvement in worst slack at 99.86% yield over deterministic optimization.
Starting Page	1029
Ending Page	1036
File Size	308718
Page Count	8
File Format	PDF
ISBN	078039254X
DOI	10.1109/ICCAD.2005.1560213
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Runtime Manufacturing Statistical distributions Performance analysis Probability Performance loss Circuit optimization Delay lines Circuit simulation
Content Type	Text
Resource Type	Article

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Gate sizing using incremental parameterized statistical timing analysis

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