NDLI: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, A. Kunhyuk Kang Roy, K.
Copyright Year	2005
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Agarwal, A.; Kunhyuk Kang; Roy, K.)
Abstract	In this paper we propose an accurate estimation and modeling of total circuit leakage distribution, considering both inter- and intra-die variations (variation in L, T/sub ox/ and random dopant fluctuation). Since, the total leakage in a circuit depends on leakage in a transistor, integration of transistors in a logic gate, and the gate topology in a circuit block, we model the total circuit leakage distribution at all levels of circuit design, while taking the different correlations among transistors, logic gates, circuit topology, and input vectors into account. The proposed model accurately estimates both statistical information (mean and variance) and the shape of the leakage distribution. We have verified the model using Monte Carlo simulation using devices of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on individual components of total leakage.
Starting Page	736
Ending Page	741
File Size	541615
Page Count	6
File Format	PDF
ISBN	078039254X
DOI	10.1109/ICCAD.2005.1560162
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leakage current Logic gates Logic design Logic circuits Circuit topology Threshold voltage Semiconductor process modeling Circuit synthesis Nanoscale devices Semiconductor device modeling
Content Type	Text
Resource Type	Article

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