NDLI: IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs

Content Provider	IEEE Xplore Digital Library
Author	Tung-Chieh Chen Yao-Wen Chang Shyh-Chang Lin
Copyright Year	2005
Description	Author affiliation: Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan (Tung-Chieh Chen; Yao-Wen Chang; Shyh-Chang Lin)
Abstract	We present in this paper, a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilevel framework that adopts the "V-cycle" framework: bottom-up coarsening followed by top-down uncoarsening, in contrast, IMF works in the "/spl Lambda/-cycle" manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on mm-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and thus the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. We also propose an accelerative fixed-outline floorplanning (AFF) to speed up wirelength minimization under the outline constraint. Experimental results show that IMF consistently obtains the best floorplanning results with the smallest wirelength for large-scale building-module designs, compared with all publicly available floorplanners. In particular, IMF scales very well as the circuit size increases. The /spl Lambda/-cycle multilevel framework outperforms the V-cycle one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the /spl Lambda/-cycle framework considers the global configuration first and then processes down to local ones level by level and thus the global effects can be handled at earlier stages. The /spl Lambda/-cycle multilevel framework is general and thus can be readily applied to other problems.
Starting Page	159
Ending Page	164
File Size	289724
Page Count	6
File Format	PDF
ISBN	078039254X
DOI	10.1109/ICCAD.2005.1560057
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Integrated circuit interconnections Clustering algorithms Design engineering Merging Chip scale packaging Transistors Law Legal factors Simulated annealing
Content Type	Text
Resource Type	Article

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