NDLI: A statistical gate-delay model considering intra-gate variability

Content Provider	IEEE Xplore Digital Library
Author	Okada, K. Yamaoka, K. Onodera, H.
Copyright Year	2003
Description	Author affiliation: Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan (Okada, K.; Yamaoka, K.; Onodera, H.)
Abstract	This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly influences the circuit-delay variation, it is important to characterize each gate-delay variation accurately. Furthermore, as every transistor in a gate affects the transient characteristics of the gate, it is also necessary to consider the intra-gate variability in the model of gate-delay variation. This effect is not captured in existing statistical delay analyses. The proposed model considers the intra-gate variability through the introduction of sensitivity constants. The accuracy of the model is evaluated, and some simulation results for circuit delay variation are presented.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	908
Ending Page	913
File Size	485868
Page Count	6
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159782
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Fluctuations Timing Semiconductor device modeling Circuit simulation Permission Delay effects CMOS integrated circuits CMOS technology Integrated circuit technology Degradation
Content Type	Text
Resource Type	Article

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