NDLI: Performance optimization of latency insensitive systems through buffer queue sizing of communication channels

Content Provider	IEEE Xplore Digital Library
Author	Ruibing Lu Cheng-Kok Koh
Copyright Year	2003
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Ruibing Lu; Cheng-Kok Koh)
Abstract	This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in the physical design stage. It can be shown that proper queue sizing can reduce or even completely avoid the performance loss due to imbalanced relay stations insertion in reconvergent paths. Moreover, the problem of queue sizing and placement of the additional buffers for maximum performance is formulated and studied to properly allocate available chip areas in the layout to communication channels. An algorithm based on mixed integer linear programming is proposed. Experimental results show that queue sizing is effective in improving the performance of latency insensitive systems even under tight area constraints. Moreover, the proposed algorithm is sufficiently efficient in obtaining the optimal solution for systems of practical sizes.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	227
Ending Page	231
File Size	401509
Page Count	5
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Optimization Communication channels Delay estimation Relays Integrated circuit interconnections Clocks Timing Pipelines Permission Robustness
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels (2003)

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels,” iccad (2003).

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

Recovery-based resilient latency-insensitive systems

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Performance analysis of latency-insensitive systems

Performance analysis and optimization of latency insensitive systems

Performance-driven constructive placement

Theory of latency-insensitive design

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels

Similar Documents

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels (2003)

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels,” iccad (2003).

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

Recovery-based resilient latency-insensitive systems

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Performance analysis of latency-insensitive systems

Performance analysis and optimization of latency insensitive systems

Performance-driven constructive placement

Theory of latency-insensitive design

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels