NDLI: On application of output masking to undetectable faults in synchronous sequential circuits with Design-For-Testability logic

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I. Reddy, S.M.
Copyright Year	2003
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA (Pomeranz, I.)
Abstract	Design-for-testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	867
Ending Page	872
File Size	469131
Page Count	6
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159777
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Sequential circuits Circuit faults Logic design Electrical fault detection Fault detection Circuit testing Design for testability Logic testing Logic circuits Sequential analysis
Content Type	Text
Resource Type	Article

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