NDLI: An enhanced multilevel algorithm for circuit placement

Content Provider	IEEE Xplore Digital Library
Author	Chan, T.F. Jason Cong Tim Kong Shinnerl, J.R. Sze, K.
Copyright Year	2003
Description	Author affiliation: Math. Dept., UCLA, Los Angels, CA, USA (Chan, T.F.)
Abstract	This paper presents several important enhancements to the recently published multilevel placement package mPL. The improvements include (i) unconstrained quadratic relaxation on small, noncontiguous subproblems at every level of the hierarchy; (ii) improved interpolation (declustering) based on techniques from algebraic multigrid (AMG), and (iii) iterated V-cycles with additional geometric information for aggregation in subsequent V-cycles. The enhanced version of mPL, named mPL2, improves the total wirelength result by about 12% compared to the original version. The attractive scalability properties of the mPL run time have been largely retained, and the overall run time remains very competitive. Compared to GORDIAN-L-DOMINO on uniform-cell-size IBM/ISPD98 benchmarks, a speed-up of well over 8/spl times/ on large circuits (/spl ges/100,000 cells or nets) is obtained along with an average improvement in total wirelength of about 2%. Compared to Dragon on the same benchmarks, a speed-up of about 5/spl times/ is obtained at the cost of about 4% increased wirelength. On the recently published PEKO synthetic benchmarks, mPL2 generates surprisingly high-quality placements-roughly 60% closer to the optimal than those produced by Capo 8.5 and Dragon-in run time about twice as long as Capo's and about 1/10th of Dragon's.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	299
Ending Page	306
File Size	569372
Page Count	8
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Algorithm design and analysis Scalability Circuit analysis computing Timing Computer science Mathematics Design automation Packaging Interpolation Costs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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