NDLI: Multi-domain clock skew scheduling

Content Provider	IEEE Xplore Digital Library
Author	Ravindran, K. Kuehlmann, A. Sentovich, E.
Copyright Year	2003
Description	Author affiliation: California Univ., Berkeley, CA, USA (Ravindran, K.; Kuehlmann, A.)
Abstract	The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner. This results in a significant limitation of the optimization potential. As an alternative, the application of multiple clocking domains with dedicated phase shifts that are implemented by reliable, possibly expensive design structures can overcome these limitations and substantially increase the implementable optimization potential of clock adjustments. In this paper we present an algorithm for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within-domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Our experiments demonstrate that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	801
Ending Page	808
File Size	673716
Page Count	8
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159768
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Clocks Delay Processor scheduling Circuits Registers Scheduling algorithm Permission Frequency Timing Upper bound
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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