NDLI: Performance efficiency of context-flow system-on-chip platform

Content Provider	IEEE Xplore Digital Library
Author	Beidas, R. Jianwen Zhu
Copyright Year	2003
Description	Author affiliation: Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Beidas, R.; Jianwen Zhu)
Abstract	Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective programming model, while not taking full advantage of the almost unlimited on-chip bandwidth. In this paper, we propose a new programming model, called context-flow, that is simple, safe, highly parallelizable yet transparent to the underlying architectural details. An SOC platform architecture is then designed to support this programming model, while fully exploiting the physical proximity between the processing elements. We demonstrate the performance efficiency of this architecture over bus based and packet-switch based networks by two case studies using a multi-processor architecture simulator.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	356
Ending Page	361
File Size	477500
Page Count	6
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159711
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	System-on-a-chip Network-on-a-chip Parallel programming Context modeling Computer architecture Computer networks Bandwidth Data structures Process design Application software
Content Type	Text
Resource Type	Article

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