NDLI: A new generation of interconnect technology for high performance electronics

Content Provider	IEEE Xplore Digital Library
Author	Kasem, M.
Copyright Year	1999
Description	Author affiliation: Vishay Siliconix Inc., Santa Clara, CA, USA (Kasem, M.)
Abstract	Vishay Siliconix's TrenchFET/sup R/ power MOSFET technology is the result of scaling MOS device dimensions and improving fabrication processes. To fully utilize this new technology in applications involving computer and mobile communication electronics, TrenchFETs must be encapsulated in a compatible miniaturized surface mount package. Consequently, Vishay Siliconix has developed the industry's first surface mount devices with sub-m/spl Omega/ package resistance. This paper presents major performance aspects of modern power MOSFET technology with emphasis on the 32 million-cell trench technology. In addition, we highlight the development methodology and characteristics of new packages that have been used to attain maximum performance. In the course of developing advanced power MOS packages, a 3D finite element study revealed that connecting the MOSFET chip with a limited number of source wire bonds could not guarantee uniformity of current density or voltage distribution across the die's top metal. Emphasis was directed toward optimization of the contact area between package and device surface metallization. Results show that a newly developed 8-lead SOIC package has superior electro-thermal performance when compared with its standard counterparts. A new bonding scheme and a Ni-based metallization process has been developed which enables the device electrical resistance to be reduced by 50%. Also, the new package has over a twofold improvement in power dissipation capability compared to its standard counterparts. This enhancement in performance has been achieved with no increase in manufacturing cost or change in package outline.
Starting Page	440
Ending Page	447
File Size	1853799
Page Count	8
File Format	PDF
ISBN	0780355024
ISSN	10898190
DOI	10.1109/IEMT.1999.804857
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-19
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface resistance MOSFET circuits Power MOSFET Electronics packaging Metallization MOS devices Fabrication Surface-mount technology Application software Computer applications
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Miniaturization of circuit protection devices to meet surface mount applications

Component attachment in lithographic film circuits

Pb-free Sn/3.5Ag electroplating bumping process and under bump metallization (UBM)

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Packaging alternatives for high lead count, fine pitch, surface mount technology

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New generation thin plastic packages delivers higher levels of power and reliability performance for power IC devices

Improved Electrical Performance Required for Future MOS Packaging

A new surface mount power package

A new generation of interconnect technology for high performance electronics

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