NDLI: Reliability evaluation of probe-before-bump technology

Content Provider	IEEE Xplore Digital Library
Author	Qing Tan Beddingfield, C. Mistry, A.
Copyright Year	1999
Description	Author affiliation: Semicond. Product Sector, Motorola Inc., USA (Qing Tan)
Abstract	As flip chip applications gain in popularity, integration of wafer bumping and probing is becoming necessary. Wafers are usually probed after bumping, but probe-after-bump technology suffers from low throughput and high cost, and also delays wafer yield feedback to the fab. However, probe-before-bump offers excellent process integration. In this paper, the authors used electroless bumping technology to study the feasibility of probe-before-bump technology. Two probe solutions, probe on under bump metallization (UBM) or probe on Al bond pad, are investigated. Between the two methods, probe-on-Al offers better fab-to-packaging flow. However, probe damage on the UBM or bond pad may have negative impact on bump structural integrity, degrading assembly reliability performance. Three sets of experiments were carried out to study the probe process. Variables evaluated included: probe process, temperature, baking, overdrive and probe card type. Results show that probe-on-Ni/Au leaves almost undetectable probe marks on the UBM and probe-on-Al can result in heavy probe marks when a high overdrive is used. Samples from each experimental set were assembled on organic substrates and tested for AATC at -40/spl deg/C to 125/spl deg/C. Thermal cycling results show that neither probe-on-Al nor probe-on-Ni/Au degrades reliability performance unless there is need for a high temperature data retention bake. If the device requires a data retention bake, probe-on-Ni/Au with low overdrive provides acceptable performance. At elevated temperature, probe-on-Ni/Au using a membrane probe card provides similar reliability performance to the unprobed group.
Starting Page	320
Ending Page	324
File Size	622884
Page Count	5
File Format	PDF
ISBN	0780355024
ISSN	10898190
DOI	10.1109/IEMT.1999.804839
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-19
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Probes Gold Temperature Assembly Flip chip Throughput Costs Delay Feedback Metallization
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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