NDLI: Reducing complexity of wafer flow to improve quality and throughput in a single-wafer cluster tool

Content Provider	IEEE Xplore Digital Library
Author	Oh, H.L.
Copyright Year	1999
Description	Author affiliation: Silicon Valley Group Inc., San Jose, CA, USA (Oh, H.L.)
Abstract	A single-wafer cluster tool refers to a group of single-wafer process modules organized around a group of wafer transporters to perform a series of process steps on a wafer. To achieve high throughput, redundant modules and transporters are added to the cluster tool. The networking of the many redundant modules and transporters brings about complex wafer flow which requires complex coordination of wafer processing and transporting. Invariably, delays occur in transporting the wafer. If the delays occur at a gating module, the throughput slows down. If they occur in critical process modules, the on-wafer results are adversely affected. Furthermore, the process results will not be consistent because the wafers are not processed in similar flow paths. This paper presents a method for reducing the wafer flow complexity. By introducing "planned delays" to the process times of noncritical process modules, it is shown that (a) zero transport delays can be assured in gating modules and critical process modules; (b) periodicity can be introduced into the wafer flow. The consequence of (a) is an improvement in quality and throughput. The consequence of (b) is a drastic reduction in the number of possible wafer flow paths, thus ensuring consistent process results. A real life example of queueing to reduce the complexity in a photoresist processing system is presented to illustrate the concept and methodology.
Starting Page	378
Ending Page	388
File Size	705468
Page Count	11
File Format	PDF
ISBN	0780355024
ISSN	10898190
DOI	10.1109/IEMT.1999.804849
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-19
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Delay Design engineering Robustness Silicon Mechanical engineering Biographies Fellows Technology management Testing
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Single-wafer cluster tool performance: an analysis of throughput

A wafer-handling interface under processing ambient conditions for a single-wafer cluster tool

Impact of wafer probe damage on flip chip yields and reliability

Reducing the overkills and retests in wafer testing process

Thru-silicon interconnect technology

First Wafer Delay and setup: How to measure, define and improve First Wafer Delays and setup times in semiconductor fabs

Single Wafer Management for Non Productive Wafers NPW

Effect of pad’s surface deformation and oscillation on monocrystalline silicon wafer surface quality

Scheduling of Single-Arm Multi-cluster Tools With Wafer Residency Time Constraints in Semiconductor Manufacturing

Reducing complexity of wafer flow to improve quality and throughput in a single-wafer cluster tool

Similar Documents

Single-wafer cluster tool performance: an analysis of throughput

A wafer-handling interface under processing ambient conditions for a single-wafer cluster tool

Impact of wafer probe damage on flip chip yields and reliability

Reducing the overkills and retests in wafer testing process

Thru-silicon interconnect technology

First Wafer Delay and setup: How to measure, define and improve First Wafer Delays and setup times in semiconductor fabs

Single Wafer Management for Non Productive Wafers NPW

Effect of pad’s surface deformation and oscillation on monocrystalline silicon wafer surface quality

Scheduling of Single-Arm Multi-cluster Tools With Wafer Residency Time Constraints in Semiconductor Manufacturing

Reducing complexity of wafer flow to improve quality and throughput in a single-wafer cluster tool