NDLI: Evaluation of eutectic solder bump interconnect technology

Content Provider	IEEE Xplore Digital Library
Author	Beddingfield, C. Qing Tan Mistry, A.
Copyright Year	1999
Description	Author affiliation: Motorola Inc., Austin, TX, USA (Beddingfield, C.)
Abstract	This paper describes the electroplated solder bump process and provides results from evaluations of the reliability performance and mechanical integrity of the bump interconnect technology for direct chip attach applications. Evaluations include studying the effects of several variables, including (a) the solder bump volume (determined by bump height and diameter), (b) the integrated circuit bond pad configuration (using various passivation opening and under bump metallization diameters), (c) the UBM stud thickness and (d) the underfill material type. The analysis of each of these variables as main effects and, in most cases, interaction effects was achieved by performing mechanical and environmental testing, including solder bump and under bump metallization (UBM) shear strength, die tensile pull, air-to-air temperature cycling (AATC) at a range of -55/125/spl deg/C and cross-sectional analysis. The intent of this study was to determine the significance of the variables and demonstrate successful reliability performance.
Starting Page	131
Ending Page	134
File Size	544226
Page Count	4
File Format	PDF
ISBN	0780355024
ISSN	10898190
DOI	10.1109/IEMT.1999.804807
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-19
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Performance analysis Integrated circuit reliability Integrated circuit technology Bonding Passivation Integrated circuit metallization Inorganic materials Performance evaluation Circuit testing
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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