NDLI: The influence of leadframe on passivation cracks growth

Content Provider	IEEE Xplore Digital Library
Author	He, Y.T. Zhang, G.Q. van Driel, W.D. Fan, X.J. Ernst, L.J.
Copyright Year	2003
Description	Author affiliation: Philips Res., Eindhoven, Netherlands (He, Y.T.; Zhang, G.Q.)
Abstract	Passivation layer in the IC interconnect has a very small feature size comparing with the global package size. When using, Finite Element Modelling (FEM) to analyse the passivation cracks, the effect of leadframes are usually neglected. In this paper, the influence of leadframes on the passivation crack growth is studied by J-integral theory using a certain leadframe thickness model with different crack lengths, different crack starting positions and different crack directions. For different critical process steps, here the final process temperature is acted as a representative parameter to analyse its impact. Yielding stress and thickness of leadframe are the design variables, wherein J-integral values of crack with certain crack lengths and different crack directions were gained Furthermore, Response Surface Model (RSM) of J-integral is established using the two leadframe design parameters. Since the yielding stresses of leadframes are strongly process dependent and probabilistic in nature, a histogram is derived to understand the probability of the J-integral under the given distribution of yielding stresses. Results show that the leadframe will make the passivation crack grow much more easily.
Sponsorship	Chinese Inst. of Electron
Starting Page	430
Ending Page	437
File Size	522400
Page Count	8
File Format	PDF
ISBN	0780381688
DOI	10.1109/EPTC.2003.1298775
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Passivation Thermomechanical processes Lead Thermal stresses Integrated circuit packaging Finite element methods Temperature Integrated circuit interconnections Silicon Residual stresses
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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