NDLI: Advances in lithography technologies for wafer-level packaging

Content Provider	IEEE Xplore Digital Library
Author	Pelzer, R. Kettner, P. Lindner, P. Schaefer, C.
Copyright Year	2003
Description	Author affiliation: EV Group, Schaerding, Austria (Pelzer, R.; Kettner, P.; Lindner, P.; Schaefer, C.)
Abstract	With the continuous reduction in IC feature size, the increased demand for higher speed and lower power consumption and with the simultaneous increase of I/O, wafer-level packaging is today an interesting solution for IC and micro electro mechanical systems(MEMS) packaging having as result the cost decrease and increased performance. With wafer-level packaging (WLP) the die and the package are fabricated and tested on the wafer prior to the dicing. Among the advantages of WLP are smaller IC package and a significant of-scale cost reduction due to high throughput of the parallel running packaging and electrical testing steps on wafer size. Thick resist-coating, lithography and wafer-to-wafer alignment for subsequent bonding are key enabling technologies for WLP. The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. This fact makes specialized and unique processing equipment development a must. This paper is summarizing the specific process requirements and will review the current technologies supporting WLP.
Sponsorship	Chinese Inst. of Electron
Starting Page	126
Ending Page	129
File Size	352390
Page Count	4
File Format	PDF
ISBN	0780381688
DOI	10.1109/EPTC.2003.1298707
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lithography Wafer scale integration Integrated circuit packaging High speed integrated circuits Costs Energy consumption Throughput Circuit testing Integrated circuit testing Wafer bonding
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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