NDLI: Solder bumps layout design and reliability enhancement of wafer level packaging

Content Provider	IEEE Xplore Digital Library
Author	Chang-Ming Liu Kuo-Ning Chiang
Copyright Year	2003
Description	Author affiliation: Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Chang-Ming Liu)
Abstract	In the design and manufacturing process of electric packaging, solder joint are generated with a variety of methods to provide both mechanical and electrical connection for applications such as flip chip, wafer bevel packaging, fine pitch ball grid array (BGA), and chip scale packaging (CSP). Solder joint shape prediction method has been incorporated as a design tool to enhance the reliability of the wafer level packaging. Wafer level chip-scale-packaging (WLCSP) is expected to be widely used in static-dynamic random access' memory (SDRAM) for its higher electrical performance and lower manufacturing costs. However, reliability of solder joints for large chip size such as 6mm /spl times/ 6mm without underfill assembly is still in question. In conventional WLCSP, the dimension of each solder ball and each solder pad is the same. The maximum thermally induced stress/strain would occur on the die-side surface of the solder joint that are located farthest away the chip center. In this research, a hybrid method combined analytical algorithm and energy-based method is applied to predict standoff heights and geometry profiles of solder balls. A hybrid-pad-shape (HPS) system is also proposed to design solder ball layout and to enhance the reliability of solder joints. The HPS system contains two kinds of solder volume and pad diameters as well as their relative location during reflow process. Next, a commercial finite element code ANSYS is applied to simulate the stress/strain behavior of the solder balls in WLCSP under temperature cycling conditions. In addition, a nonlinear and parametric finite element analysis is conducted to, investigate the reliability issues that result from several design parameters including solder joint layout, solder volume, pad diameter, die/substrate thickness, and thickness, material properties of stress buffer layer (SBL). The results reveal that as the WLCSP contains larger solder balls located at corner area underneath the chip, the maximum equivalent plastic strain of the solder joints would be evidently reduced and the solder joint reliability under thermal loading would be highly enhanced On the other hand, thinner die and thicker SBL are also good for the reliability of the WLCSP. Furthermore, the findings presented in this research can be used as a design guideline for area array interconnections such as CSP, flip chip packaging, Super CSP and fine pitch BGA.
Sponsorship	Chinese Inst. of Electron
Starting Page	56
Ending Page	64
File Size	709175
Page Count	9
File Format	PDF
ISBN	0780381688
DOI	10.1109/EPTC.2003.1298693
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Soldering Chip scale packaging Thermal stresses Capacitive sensors Flip chip Finite element methods Process design Manufacturing processes Mesh generation
Content Type	Text
Resource Type	Article

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