NDLI: A [100] silicon stress test chip with optimized piezoresistive sensor rosettes

Content Provider	IEEE Xplore Digital Library
Author	Jaeger, R.C. Suhling, J.C. Anderson, A.A.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. & Mech. Eng., Auburn Univ., AL, USA (Jaeger, R.C.; Suhling, J.C.)
Abstract	A new piezoresistive stress sensing test chip for use on (100) silicon wafers is discussed. The die design contains four-element dual-polarity rosettes optimized for use in measurement of the in-plane normal stress difference (/spl sigma//sub 11//sup '/-/spl sigma//sub 22//sup '/) and the in-plane shear stress /spl sigma//sub 12//sup '/. The rosettes offer high sensitivity to stress since their outputs are proportional to the largest piezoresistive coefficients, /spl pi//sub 44/ in p-type silicon and /spl pi//sub D/ in the n-type silicon. The rosette outputs are both temperature compensated and insensitive to rotational alignment errors and are independent of the out-of-plane normal stress /spl sigma//sub 33/'. Thus, they may be used to measure the in-plane stress components in plastic encapsulated packages where /spl sigma//sub 33/' is not zero. Three-element off-axis p-type and n-type rosettes are also included on each chip for use in uniaxial calibration of the required piezoresistive coefficients. The properties of these rosettes are reviewed, and it is shown that the off-axis rosette yields temperature compensated calibration of the values of /spl pi//sub 44/ and /spl pi//sub D/.<>
Starting Page	741
Ending Page	749
File Size	791150
Page Count	9
File Format	PDF
ISBN	0780309146
DOI	10.1109/ECTC.1994.367587
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Testing Piezoresistance Stress measurement Calibration Resistors Thermal stresses Temperature sensors Packaging Semiconductor device measurement
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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