NDLI: A test chip design for detecting thin film cracking in integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Gee, S.A. Johnson, M.R. Chen, K.L.
Copyright Year	1994
Description	Author affiliation: Nat. Semicond. Corp., Santa Clara, CA, USA (Gee, S.A.; Johnson, M.R.; Chen, K.L.)
Abstract	A reliability problem associated with integrated circuit assembly in molded plastic packages involves cracking in the deposited thin film layers on the top silicon surface. During thermal cycle testing, thermo-mechanical stresses resulting from differences in expansion coefficient can cause large relative displacements at the silicon/mold compound interface. This paper reports on a test chip design involving a matrix of crossing metal traces. This test chip has been designed to be sensitive to electrical leakage problems associated with thin film cracking. Two important quantities are measured. The first is electrical failure rate - which is determined as a function of metal width and proximity to the corners and edges of the die. The second is the extent over which cracking in the thin film layers progresses into the interior of the die. When overlaid on simple linear elastic finite elements models of stress, this locus of failure tends to follow lines of constant shear stress. This allows the assignment of a nominal stress value, critical in the collapse of microscopic thin film structures.<>
Starting Page	1050
Ending Page	1057
File Size	945454
Page Count	8
File Format	PDF
ISBN	0780309146
DOI	10.1109/ECTC.1994.367499
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Transistors Circuit testing Plastic films Thin film circuits Silicon Thermal stresses Integrated circuit reliability Assembly Plastic integrated circuit packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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