NDLI: A new stress chip design for electronic packaging applications

Content Provider	IEEE Xplore Digital Library
Author	Hau, W.L.W. Yuen, M.M.F. Yan, G.Z. Chan, P.C.H.
Copyright Year	2000
Description	Author affiliation: Dept. of Mech. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China (Hau, W.L.W.)
Abstract	Stress sensing chips are invaluable for structural analysis of electronic packages, and can be used for in-situ real-time measurement of thermally induced die surface stress. Four-point-bending calibration, wafer-level calibration and hydrostatic calibration have been used to calibrate the stress sensing chip. These methods are used to calibrate different piezoresistive coefficients B/sub 1/, B/sub 2/ or their combinations (B/sub 1/-B/sub 2/), (B/sub 1/+B/sub 2/) and (B/sub 1/+B/sub 2/+B/sub 3/). Hydrostatic calibration is a bottleneck to quick calibration. Only one chip can be calibrated at a time and it must be wire bonded. Also, the value of coefficients (B/sub 1/+B/sub 2/+B/sub 3/) obtained is not temperature compensated and precise temperature measurement is required. Thus, a quick and accurate calibration method is key to making stress sensing chips more acceptable for electronic packaging use. In this paper, a new (111) stress sensing chip design is presented, and an innovative calibration scheme is proposed. Calibration can be done at wafer level, giving large savings in calibration time over the die form process. The mechanism is based on thermal expansion of the Al micro-beams which produce out-of-plane shear stresses on the sensing elements under temperature change. The relationship of normalized resistance change against temperature was found experimentally. Stresses produced by the Al micro-beam are high enough for calibration, with 4.6/spl sim/5.4% difference of normalized resistance changes between resistors with and without micro-beam. Also, a simple 1D model was proposed to estimate the order of magnitude of the stress under temperature change.
Starting Page	457
Ending Page	463
File Size	619797
Page Count	7
File Format	PDF
ISBN	0780366549
DOI	10.1109/EMAP.2000.904199
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Electronics packaging Calibration Thermal stresses Electronic packaging thermal management Temperature sensors Wafer scale integration Stress measurement Semiconductor device measurement Piezoresistance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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