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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sung Dae Suk Sung-Young Lee Sung-Min Kim Eun-Jung Yoon Min-Sang Kim Ming Li Chang Woo Oh Kyoung Hwan Yeo Sung Hwan Kim Dong-Suk Shin Kwan-Heum Lee Heung Sik Park Jeorig Nam Han Park, C.J. Jong-Bong Park Dong-Won Kim Donggun Park Byung-Il Ryu |
| Copyright Year | 2005 |
| Description | Author affiliation: Device Res. Team, Samsung Electron. Co., Gyeonggi-Do (Sung Dae Suk; Sung-Young Lee; Sung-Min Kim; Eun-Jung Yoon; Min-Sang Kim; Ming Li; Chang Woo Oh; Kyoung Hwan Yeo; Sung Hwan Kim) |
| Abstract | For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs |
| Starting Page | 717 |
| Ending Page | 720 |
| File Size | 650742 |
| Page Count | 4 |
| File Format | |
| ISBN | 078039268X |
| DOI | 10.1109/IEDM.2005.1609453 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | MOSFET circuits Fabrication Silicon compounds Silicon germanium Germanium silicon alloys Etching CMOS process Annealing Research and development Nanoscale devices |
| Content Type | Text |
| Resource Type | Article |
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