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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Srivastava, N. Joshi, R.V. Banerjee, K. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA (Srivastava, N.) |
| Abstract | This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30% |
| Starting Page | 249 |
| Ending Page | 252 |
| File Size | 711821 |
| Page Count | 4 |
| File Format | |
| ISBN | 078039268X |
| DOI | 10.1109/IEDM.2005.1609320 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Thermal management Carbon nanotubes Power dissipation Energy management Integrated circuit interconnections Copper Delay Very large scale integration Current density Temperature |
| Content Type | Text |
| Resource Type | Article |
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