Fabrication and electrical properties of local damascene finfet cell array in sub-60nm feature sized dram.

The application of BT-FinFET technology for sub 60nm DRAM integration

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Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond

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Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

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Comparative study of $p^{+}/n^{+}$ gate modified Saddle MOSFET and $p^{+}/n^{+}$ gate bulk FinFETs for sub-50 nm DRAM cell transistors

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$hbox{n}^{+}/hbox{p}^{+}$ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

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Data retention time in DRAM with WSi/sub x//P/sup +/poly-Si gate NMOS cell transistors

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A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

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Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

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