NDLI: High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Content Provider	IEEE Xplore Digital Library
Author	Sung Dae Suk Kyoung Hwan Yeo Keun Hwi Cho Ming Li Yun Young Yeoh Sung-Young Lee Sung Min Kim Eun Jung Yoon Min Sang Kim Chang Woo Oh Sung Hwan Kim Dong-Won Kim Donggun Park
Copyright Year	2002
Abstract	A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.
Sponsorship	IEEE Nanotechnology Council
Starting Page	181
Ending Page	184
Page Count	4
File Size	660080
File Format	PDF
ISSN	1536125X
Volume Number	7
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Transistors Silicon compounds Etching Shape Hydrogen Annealing Silicon germanium Germanium silicon alloys Tin 5 nm Bulk MOSFET gate all around (GAA) high performance MOSFET nanowire TSNWFET twin silicon nanowire 5nm Twin Silicon nanowire gate all around bulk MOSFET
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High performance twin silicon nanowire MOSFET(TSNWFET) on bulk si wafer

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the $Y$ -Function Technique

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Similar Documents

High performance twin silicon nanowire MOSFET(TSNWFET) on bulk si wafer

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the $Y$ -Function Technique

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer